上海诺基亚西门子微波内部推荐

bengier1986 · 发表于 2010-2-5 15:52:19

2 for SE
6 for HW
16 for SW
8 for SVT

The breakdown details are listed below.

System Engineer 2 with JG8 or JG9

MWR R&D - System design engineer

Key Responsibilities:
l Product requirement analysis and product implementation planning
l Interface definition and agree with the development parties
l Product architecture design and high level specifications

Job Requirements:
l Solid background in Cellular networks, PDH, SDH and/or IP/Ethernet packet data technologies.
l Be Able to understand and handle bigger entities and dependencies between them
l Good speaking and writing skills in English.

Hardware Engineer 1 JG8 Circuit Designer and 5 JG8 FPGA Engineers

MWR R&D - HW Design Engineer

Key Responsibilities:
l         Control the detailed board-level logic and schematic design including component selection according to company policies.
l         Cooperate with category managers, suppliers and other relevant functions to solve technical issues for quality
l         Supervision of layout designs according to design rules. Bring-up, debug, and design characterization/verification.
l        &nbsp

repare product documentations and support to manufacturing transition.

Job Requirements:
l         3+ years experience taking board-level products successfully from design to production
l         Design background in PDH, SDH or packet based telecommunication equipment
l         Experience in high-speed DAC and ADC, PLL, AFE, LPF and Amplifier circuit design.
l         Experience in Digital logic design (e.g. high-speed bus and clock termination and PLL clock drivers).
l         Knowledge of different kinds of power design (e.g. booster, inverter and step down converter) is a plus.

MWR R&D - FPGA Design Senior Engineer

Key Responsibilities:
l Participate in outlining product architecture definition and derive the functional specification for FPGA functionality level.
l Work as the technical point of contact on the FPGA area.

Job Requirements:
l Be able to generate block level definitions and FPGA requirements for the design team
l Complete understanding of the FPGA design flow.
l Knowledge of FPGA-Design and Formal Verification tools. Good VHDL experience
l With TDM or Packet based FPGA design experience more than 2 years.

Software Engineer 4x JG7 or JG8 Platform Software, 5x JG7 or JG8 Application Software, 6 x JG7 or JG8 Ethernet Driver & Protocol, 1 x JG8 Integration Test SW
MWR R&D - Embedded SW design engineer Operating System

Key Responsibilities:
l          Development of the embedded SW for telecommunication transmission units
l          Participate in outlining product architecture definition and derive the low level SW specification

Job Requirements:
l          Have C and C++ programming skill. Knowledge of software dev process
l          Experience of the basic SW tools: Compilers (e.g. Diab, GNU), ClearCase, debug environments and testing tool (e.g. scripts, HiT)
l          Be familiar with RT OS knowledge link VxWorks, Linux or OSE
l          Developing and debugging software on embedded platform like Freescale or the others

MWR R&D - Ethernet Driver Development Software Engineer

Job Description:        
l Be responsible for driver development for Ethernet or Datacom function.
 
Job Requirements:
l Experience in multi-task RTOS (VxWorks preferred), C/C++, TCP/IP in real time embedded system, and distributed design.
l Hands on experience in firmware / driver development on Datacom / Telecom equipment. 

SVT Engineer 8 x JG7 or JG8

MWR R&D - System Test Engineer

Key Responsibilities:
l Responsible for telecommunication device test execution, testing reporting and analysis.
l Ensure effective testing and high quality product delivery.
l Protocol testing (SW feature level verification), functional testing (overall feature in different system configurations) and performance testing (environmental, EMC, safety) related persons needed.

Job Requirements:
l 2+ years of experience in the R&D of Telecommunication Networks or Communication industry. Familiar with at least two of the following protocols: PDH, SDH, Ethernet, MPLS.
l Familiarity with test tool and communication testing devices (PDH, SDH, packet) such as Agilent, Smart Bits, etc.
l Experience of writing test suites and test procedures at the black box and system test levels.