关于#模块测试#的问题：无论改成module还是program都不行
一直报错，无论改成module还是program都不行，一直编译错误vlab4/factory_overide
1ho 日 module factory override;
1h1 Regi...In import uvm pkg::*;
@mC... mcd... include "uvm macros.svh"
AsS...
ECLASS COML EXTEND UVMCOMPONENT:
String INmcdf... uvm component utils(coml)
FUNCTION NEW(STRIN NAME ="COML" UVM COMPONENT PARENTNULL):
MPARENT):
Sdisplay(SSformAtf("*s is created"NAME)）:
endfunction
10 VIRTUAL fUNCTION VOID HELLO (STRING nAmE):
11 Sdisplay(Ssformatf("compl:: *s said hello"，name)）:
la endfunction
13 CLASS COM2 EXTENDS COML:
14 uvm_ component utils(com2)
155
FUNCTION NEW(STRIN NAME-"COM2".UVM COMPONENT PARENT NULL):
17
WM.PARENT):
Sdisplay（gformatt（"#s is created".name)）;
endfunction
function void hello(string name):
edisplay(8formatt("com2:: *s said hello",name)）
endfunction
2 endclass
endmodule RSTN ih1 Regl...In import uvm pkg::*;
tl @MC. include "uvm macros.svh"
tests Cmc Unsuccessful Compile
name mcdf
Vlog -work Work -VOPT -sV -stAts=NONE D:/software/questasim/examples/sylab4/fact
OrY_overide.sV
QUESTASIM-64 VLOG 10.6C COMPILER 2017.07 JUL 26 2017
COMPILING moDuLE factory_overriDE
IMPORTING PACKAGE MTIUVM.UVM PKG (UVM-L.1D BUILT-IN)
AX NOTE: (VLOG-2286) D:/SOfWARE/UESTASIM/EXAMPLES/SVLAB4/fACTORY OVERIDE.3V(3)
: USIN MPLIC D:-1/VERILOGRC/UM-L.1D/
SRC FROM IMPORT UVM PKG
** ERROR: (VLOG-13069) D:/software/questasim/examples/svlab4/factory_overide.(
25): nEar "EndmOdulE": sytx error unexpected endmodule expecting function or
TASK OR*SSTEMVERILOGKEYWORD'PURE!".
那就不知道了 打个短点看下输出 代码写错了 写的语法错误
页:
[1]
